HIPStR—Heterogeneous-ISA Program State Relocation

By Ashish Venkat, Sriskanda Shamasunder, Dean M. Tullsen, and Hovav Shacham.

In Proceedings of ASPLOS 2016. ACM Press, Apr. 2016.


Heterogeneous Chip Multiprocessors have been shown to provide significant performance and energy efficiency gains over homogeneous designs. Recent research has expanded the dimensions of heterogeneity to include diverse Instruction Set Architectures, called Heterogeneous-ISA Chip Multiprocessors. This work leverages such an architecture to realize substantial new security benefits, and in particular, to thwart Return-Oriented Programming. This paper proposes a novel security defense called HIPStR—Heterogeneous-ISA Program State Relocation—that performs dynamic randomization of run-time program state, both within and across ISAs. This technique outperforms the state-of-the-art just-in-time code reuse (JIT-ROP) defense by an average of 15.6%, while simultaneously providing greater security guarantees against classic return-into-libc, ROP, JOP, brute force, JIT-ROP, and several evasive variants.



@InProceedings{VSTS16, author = {Ashish Venkat and Sriskanda Shamasunder and Hovav Shacham and Dean M. Tullsen}, title = {HIPStR---Heterogeneous-ISA Program State Relocation}, booktitle = {Proceedings of ASPLOS 2016}, year = 2016, editor = {Yuanyuan Zhou}, month = apr, publisher = {ACM Press}, pages = {727-41} }

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